New manufacturing technologies have made possible the integration of
entire systems on a single chip. This new design paradigm, termed
system-on-chip (SOC), together with its associated manufacturing
problems, represents a real challenge for designers.

SOC is
also reshaping approaches to test and validation activities. These are
beginning to migrate from the traditional register-transfer or gate
levels of abstraction to the system level. Until now, test and
validation have not been supported by system-level design tools so
designers have lacked the infrastructure to exploit all the benefits
stemming from the adoption of the system level of abstraction. Research
efforts are already addressing this issue.

This monograph
provides a state-of-the-art overview of the current validation and test
techniques by covering all aspects of the subject including:

• modeling of bugs and defects;
• stimulus generation for validation and test purposes (including timing errors;
• design for testability.